processor-features

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Pipelining

Pipelining is the process of carrying out multiple instructions concurrently
Each instruction will be at a different stage of the fetch-decode-execute cycle
One instruction can be fetched while the previous one is being decoded and the one before is being executed
In the case of a branch, the pipeline is flushed
This table shows which stage each instruction is at during each step:

While one instruction is being executed, the next instruction will be decoded and the following instruction will be fetched

RISC (Reduced Instruction Set Computer) processors are designed for pipelining efficiency
Key features that support pipelining:
- Each instruction takes one clock cycle (or close to it)
- Fixed-length instructions, making decoding easier
- Limited instruction set, reducing complexity and stage duration
- A large number of general-purpose registers, reducing memory access

Registers are fast, temporary storage inside the CPU
RISC processors rely heavily on registers for operand storage rather than accessing RAM
Intermediate values are stored in registers between stages
Register usage reduces memory bottlenecks, allowing pipelining to run smoothly
Example:
- Instruction A loads value into Register R1
- Instruction B adds R1 + R2 and stores result in R3
- All of these can be done efficiently within the CPU using registers

Advantage	Explanation
Increased throughput	Multiple instructions handled at once
Better use of CPU components	Fetch, decode, and execute units are all in use simultaneously
Reduced idle time	No waiting between stages
Faster execution of instruction stream	Even if individual instructions don’t run faster

Describe the process of pipelining during the fetch-execute cycle in RISC processors.[4]

Answer

Instructions are divided into subtasks / 5 stages [1 mark]
… Instruction fetch / IF, Instruction decode / ID, operand fetch / OF, opcode/instruction execute IE, result store / write back result / WB [1 mark]
Each subtask is completed during one clock cycle [1 mark]
No two instructions can execute their same stage at the same clock cycle [1 mark]
The second instruction begins in the second clock cycle, while the first instruction has moved on to its second subtask [1 mark]
The third instruction begins in the third clock cycle while the first and second instructions move on to their second and third subtasks, respectively, etc. [1 mark]