课 32, 主题 1

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flip-flops

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SR & JK flip flops

What are SR and JK flip flops?

In A Level Computer Science, SR (Set-Reset) and JK flip flops are digital memory components used in sequential circuits
They store 1 bit of data and are commonly used in counters, control systems, and synchronous logic
They are both types of bistable circuits, meaning:
- They have two stable states
- They respond to clock signals
- They are often edge-triggered (typically on the rising edge)

SR flip flop

SR stands for Set and Reset
An SR flip-flop can be constructed using NOR gates (common in exams)

Inputs:

S = Set
R = Reset
CLK = Clock (when edge-triggered)

Outputs:

Q = Current stored value
NOT(Q) = Inverse of Q

SR flip flop truth table (NOR logic)

S	R	Q (next state)	Description
`0`	`0`	`No change`	Memory/Hold
`0`	`1`	`0`	Reset
`1`	`0`	`1`	Set
`1`	`1`	`0`	Forces Q = 0 (NOR only)

Examiner Tips and Tricks

In NOR-based SR flip-flops, S = 1, R = 1 is not invalid, it forces Q = 0
(In NAND-based designs, this state is undefined)

SR flip flop example

Action	S	R	Q	NOT(Q)	Reasoning
Initially	`1`	`0`	`1`	`0`	Set: S = 1 forces Q = 1
S changed to 0	`0`	`0`	`1`	`0`	Memory mode: No change
R changed to 1	`0`	`1`	`0`	`1`	Reset: R = 1 forces Q = 0
R changed to 0	`0`	`0`	`0`	`1`	Memory mode: Q holds
S and R changed to 1	`1`	`1`	`0`	`0`	NOR logic forces both Q and NOT(Q) to 0 (Q = 0)

JK flip flop

The JK flip-flop is a more versatile version of the SR flip-flop
It solves the problem of the SR’s illegal state

Problem with SR	Why JK solves it
1. S = 1 and R = 1 is invalid	JK uses this condition to toggle the output instead
2. Glitches from feedback loops	JK uses a clock to control exact timing of changes

Inputs:

J = Set
K = Reset
CLK = Clock (required)

Outputs:

Q = Current state
NOT(Q) = Inverse

JK flip flop truth table

J	K	Q (next)	Description
`0`	`0`	`No change`	Memory/Hold
`0`	`1`	`0`	Reset
`1`	`0`	`1`	Set
`1`	`1`	`Toggle`	Q becomes NOT(Q)

Use cases

Flip Flop	Typical uses
SR	Simple memory, control circuits
JK	Toggles, counters, frequency dividers

Worked Example

Draw a logic circuit for an SR flip-flop and label the inputs.[3]

Simple box diagram with horizontal lines on the left, vertical lines on the right labelled Q and QI. Lines on the left have no labels.

Answer

Or

SR latch circuit diagram with two NOR gates. Inputs are labelled "R/Reset" and "S/Set," with outputs marked as Q and not-Q.

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