Computer Science GCES OCR
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Cpu Architecture Performance And Embedded Systems Ocr5 主题
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Primary And Secondary Storage Ocr6 主题
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Data Storage And Compression Ocr12 主题
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Units Of Data Storage Ocr
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Processing Binary Data Ocr
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Data Capacity And Calculating Capacity Requirements Ocr
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Converting Between Denary And Binary Ocr
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Binary Addition Ocr
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Converting Between Denary And Hexadecimal Ocr
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Converting Between Binary And Hexadecimal Ocr
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Binary Shifts Ocr
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Representing Characters Ocr
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Representing Images Ocr
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Representing Sound Ocr
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Compression Ocr
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Units Of Data Storage Ocr
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Networks And Topologies Ocr6 主题
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Wired And Wireless Networks Protocols And Layers Ocr6 主题
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Identifying And Preventing Threats To Computer Systems And Networks Ocr2 主题
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Operating Systems And Utility Software Ocr2 主题
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Ethical Legal Cultural And Environmental Impact Ocr2 主题
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Computational Thinking Searching And Sorting Algorithms Ocr3 主题
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Designing Creating And Refining Algorithms Ocr5 主题
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Programming Fundamentals And Data Types Ocr5 主题
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Additional Programming Techniques Ocr7 主题
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Defensive Design And Testing Ocr6 主题
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Boolean Logic Diagrams Ocr2 主题
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Programming Languages And Integrated Development Environments Ides Ocr3 主题
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The Exam Papers Ocr2 主题
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Structuring Your Responses Ocr3 主题
Von Neumann Architecture Ocr
Exam code:J277
Von Neumann Architecture
What is the Von Neumann architecture?
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The Von Neumann Architecture is a design of the CPU which was proposed by Mathematician John Von Neumann in the 1940s, which most general-purpose computers are built upon
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The Von Neumann Architecture outlines how the computer memory, input / output devices and processor all work together

The Von-Neumann-architecture
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It consists of 4 main registers
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The Program Counter (PC)
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The Memory Address Register (MAR)
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The Memory Data Register (MDR)
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The Accumulator (ACC)
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For each of the registers you must know
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The name of the register
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Its acronym
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The purpose of the register
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What do each of the registers do?
Program Counter (PC)
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Holds the memory address of the next instructions to be executed
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Increments by 1 as the fetch-decode-execute cycle runs
Memory Address Register (MAR)
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Holds the memory address of where data or instructions are to be fetched from
Memory Data Register (MDR)
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Stores the data or instruction which has been fetched from memory
Accumulator (ACC)
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Stores the results of any calculations that have taken place in the Arithmetic Logic Unit (ALU)
Worked Example
Complete the table by writing the missing definition or name of each of the common CPU components and registers.
|
CPU Component or Register |
Definition |
|---|---|
|
CU (Control Unit) |
|
|
|
Stores the address of the data to be fetched from or the address where the data is to be stored. |
|
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Stores the address of the next instruction to be fetched from memory. Increments during each fetch-execute cycle. |
|
Arithmetic Logic Unit // ALU |
|
[4]
Answer
|
CPU Component or Register |
Definition |
|---|---|
|
Control Unit // CU |
Sends signals to synchronise / control / coordinate the processor Decode instructions to run the F-E cycle |
|
Memory Address Register // MAR |
Stores the address of the data to be fetched from or the address where the data is to be stored. |
|
Program Counter // PC |
Stores the address of the next instruction to be fetched from memory. Increments during each fetch-execute cycle. |
|
Arithmetic Logic Unit // ALU |
Performs mathematical calculations and logical operations |
Responses